1. Field of the Invention
This invention relates to commands received by an integrated circuit and more particularly to commands which have a possibility of being canceled.
2. Description of the Related Art
In current processor implementations, a processor issues requests to a memory controller for such transactions as, e.g., read or write commands, or probe responses. In one implementation for a stand-alone processor, a command channel is provided over which the processor issues requests to another integrated circuit incorporating the memory controller. In such systems, data may be transmitted to and from the processor over a data channel that is separate from the command channel. In a typical computer system incorporating such a processor, an integrated circuit interfaces to the processor to provide both a memory control function and a bridge function between the host bus (the command and data channel) and other system buses. One of the bridge functions typically provided is a bridge between the host bus and the industry standard Peripheral Component Interconnect (PCI) bus. Such integrated circuits have been described in the art as “north bridges”.
One of the functions performed by memory controller logic on a north bridge is to probe the cache memory located on the processor in order to maintain coherence between the various components of the memory when another device, e.g., an I/O device, accesses memory. The probe determines whether the cache memory on the processor has a copy of the memory location (typically a cache line containing that memory location) about to be accessed by the I/O device. The processor responds through the command channel with a probe response indicating whether or not that particular cache line is located in the cache memory.
The command channel may be a split transaction bus in that commands such as reads may be separated from the data that is returned. Because multiple transactions may be outstanding, the processor tracks the number of outstanding transactions. The commands issued by the processor are received by the north bridge into a command queue.
The command channel may be relatively narrow, e.g., 13 bits, and therefore command/address information is sent over the command channel in multiple clock cycles. However, because certain commands are executed speculatively, a command may be canceled after a portion of the command has already been sent over the command channel. Therefore, it would be desirable to handle the cancellation of commands with a minimum effect on downstream logic.